A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories including e.g., read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). One type of EEPROM device is a flash EEPROM device (also referred to as “flash memory”).
Each nonvolatile memory device has its own unique characteristics. For example, the memory cells of an EPROM device are erased using an ultraviolet light, while the memory cells of an EEPROM device are erased using an electrical signal. In a conventional flash memory device blocks of memory cells are simultaneously erased (what has been described in the art as a “flash-erasure”). The memory cells in a ROM device, on the other hand, cannot be erased at all. EPROMs, and EEPROMs, including flash memory, are commonly used in computer systems that require reprogrammable nonvolatile memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include, e.g., portable computers, personal digital assistants (PDAs), digital cameras, portable music players, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices.
FIGS. 1A-1G depict one conventional process of forming floating gate regions for one-transistor storage cells of non-volatile memory devices.
As shown in FIG. 1A, a pad oxide layer 12 is formed on a silicon substrate 11. A nitride layer 13 is then formed on top of the pad oxide 12. Trenches 14 are formed in the resulting structure, as shown in FIG. 1B. An oxide layer 15 is deposited within the trenches 14 and on top of the nitride layer 13. The resulting structure is shown in FIG. 1C.
Standard STI chemical mechanical planarization (CMP) is used to isolate the active regions of the device. The conventional STI CMP process uses the nitride layer 13 as a stop layer. The structure resulting from the STI CMP process is illustrated in FIG. 1D. As shown in FIG. 1E, after the STI CMP process, the nitride layer 13 and the pad oxide layer 12 are stripped, thus exposing the active areas 18.
After the nitride layer 13 and pad oxide layer 12 are stripped, a gate oxide layer 16 and a polysilicon layer 17 are deposited (FIG. 1F). The polysilicon layer 17 will form the floating gate of completed one-transistor flash memory cells. As is shown in FIG. 1F, polysilicon 17 is deposited over the active areas and the oxide 15. A self aligned floating gate (SAFG) CMP process is then implemented to remove excess polysilicon 17 and to isolate the polysilicon 17 in the active areas 18.
The SAFG CMP process is very demanding. The amount of polysilicon 17 left behind over the active areas 18 depends on the field leveling in the array and periphery, oxide dishing in the periphery, array center to edge doming, and the amount of nitride remaining. Dishing refers to the thinning of a structure, caused by uneven polishing based on the selectivity of the slurry being used, resulting in a dish-like profile when measured in reference to the surrounding material. For example, when polishing oxide and stopping on nitride, the slurry used is typically selective to nitride, so when the polish hits nitride, it polishes oxide faster than nitride, resulting in a dish-like profile in the oxide at the level of the nitride. Doming is the opposite of dishing, resulting in a dome-like profile. Doming is usually caused by fill pattern issues. The SAFG CMP needs to be highly selective to the oxide 15 with good polysilicon 17 polishing rate; however, the CMP should not cause dishing in the polysilicon 17.
It is desirable to integrate the above described STI CMP and SAFG CMP steps into a single process flow to overcome the above-noted shortcomings. Accordingly, a simplified process for forming a floating gate region of the transistor storage cells of a non-volatile memory device is needed and desired.